Nand flash memory having c/a pin and flash memory system including the same

ABSTRACT

A NAND flash memory in which a command/address pin is separated from a data input/output pin. The NAND flash memory includes a memory cell array used for storing data, a command/address pin through which a command and an address are received for transmitting data in the memory cell array, and a data input/output pin through which data are transmitted in the memory cell array. The command/address pin is separated from the data input/output pin in the NAND flash memory. Data input/output speed is increased. Furthermore, the NAND flash memory can perform a bank interleaving operation with a minimal delay time.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 10-2006-0137629, filed on Dec. 29, 2006, the entirecontents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present disclosure relates to a memory device, and moreparticularly, to a NAND flash memory having a command/address (C/A) pinand a flash memory system including the same.

2. Discussion of the Related Art

Semiconductor memory devices are storage devices for storing data.Semiconductor memory devices can be classified as a random access memory(RAM) and a read only memory (ROM). A RAM is a volatile memory devicethat requires power to maintain stored data. A ROM is a nonvolatilememory device that can maintain stored data even when not powered.

Examples of RAMs include a dynamic RAM (DRAM) and a static RAM (SRAM).Examples of ROMs include a programmable ROM (PROM), an erasableprogrammable ROM (EPROM), an electrically erasable programmable ROM(EEPROM), and a flash memory. Examples of flash memories include a NORflash memory and a NAND flash memory. NAND flash memories are widelyused for mobile communication terminals, portable media players, digitalcameras, and mobile storage media.

FIG. 1 illustrates a conventional NAND flash memory 100, and FIG. 2 is atable providing descriptions of pins of the NAND flash memory 100.Referring to FIG. 1, the NAND flash memory 100 includes control pinssuch as RnB, ALE, CLE, nWE, and nCE pins that are formed on a firstsurface 110 of the NAND flash memory 100. The NAND flash memory 100further includes data pins such as DQ0 through DQ7 pins formed on asecond surface 120.

The pin structure of the NAND flash memory 100 shown in FIG. 1 is astructure for a thin small outline package (TSOP). However, since thecontrol pins are formed on one surface of the NAND flash memory 100,board structure for the NAND flash memory 100 is complicated.Furthermore, when a memory module is formed using a plurality of NANDflash memories having the pin structure illustrated in FIG. 1, thestructure of a printed circuit board (PCB) for the memory module iscomplicated.

FIG. 3 is a block diagram illustrating a flash memory system 200 havinga multi-bank architecture using the NAND flash memory 100 of FIG. 1.Referring to FIG. 3, the flash memory system 200 may include a flashcontroller 250, first bank 210, second bank 220, third bank 230, andfourth bank 240.

Each of the banks 210, 220, 230, and 240 includes four NAND flashmemories. For example, the first bank 210 includes four NAND flashmemories 211, 212, 213, and 214. The second bank 220 includes four NANDflash memories 221, 222, 223, and 224. The third bank 230 includes fourNAND flash memories 231, 232, 233, and 234. The fourth bank 240 includesfour NAND flash memories 241, 242, 243, and 244. The flash controller250 is connected to the banks 210, 220, 230, and 240 through fourchannels 1 through 4. Here, each of the channels 1 through 4 connectscorresponding NAND flash memories of the banks 210, 220, 230, and 240.For example, channel 1 connects NAND flash memories 211, 221, 231, and241 of the banks 210, 220, 230, and 240, respectively. Similarly,channel 2 connects NAND flash memories 212, 222, 232, and 242. Channel 3connects NAND flash memories 213, 223, 233, and 243, Channel 4 connectsNAND flash memories 214, 224, 234, and 244.

The controller 250 performs a bank interleaving operation using chipenable signals nCE0-nCEX (where X is a positive integer). In so doing,the controller 250 receives as many enable signals and read and busysignals RnB0-RnBX as there are NAND flash memories. As used herein, bankinterleaving is a data reading or writing operation performed betweenbanks of a memory system in which two or more banks share a commonchannel. For example, in a bank interleaving operation, the flashcontroller 250 reads data from and/or writes data to the NAND flashmemories 211, 221, 231, and 241 connected to channel 1 while movingbetween the NAND flash memories 211, 221, 231, and 241.

As described above, as many chip enable signals nCE0 to nCEX and readyand busy signals RnB0 to RnBX are used as the number of flash memorychips for a bank interleaving operation. Therefore, when the flashmemory system 200 uses all the four channels 1 to 4, sixteen chip enablesignals nCE0 to nCE15 and sixteen read and busy signals RnB0 to RnB15are used for a bank interleaving operation. Accordingly, the structureof the flash memory system 200 becomes more complicated as the numbersof banks and flash memory chips increase.

A conventional NAND flash memory receives address and command signalsthrough a data input/output (DQ) pin. Therefore, when address andcommand signals are input to the NAND flash memory, data cannot be inputto or output from the NAND flash memory. This results in a data delaytime. Data input/output is especially delayed when a bank interleavingoperation is performed.

Furthermore, when data is written to or read from a cell array of aconventional NAND flash memory, RnB signals are generated. In this case,a flash controller cannot perform any operation until thewriting/reading operation is completed. This reduces the performance ofa flash memory system.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a NAND flashmemory having fast data input/output.

Exemplary embodiments of the present invention provide a flash memorysystem that performs a bank interleaving operation while minimizingdelay time.

Exemplary mbodiments of the present invention provide NAND flashmemories including a memory cell array used for storing data, acommand/address pin through which a command and an address are receivedfor inputting data to or outputting data from the memory cell array, anda data input/output pin through which data are input to or output fromthe memory cell array.

In some exemplary embodiments, the NAND flash memory further includes astatus register receiving a status read command through thecommand/address pin and providing an operational status of the NANDflash memory to a flash controller. The flash controller sends thestatus read command to the NAND flash memory when the NAND flash memoryoperates, before the NAND flash memory operates, or after the NAND flashmemory operates. The status register sends a status signal SQ to theflash controller to inform the flash controller whether the NAND flashmemory is internally operational. The flash controller controls theinternal operation of the NAND flash memory in response to the statussignal SQ.

In some exemplary embodiments, the data is input/output through the datainput/output pin depending upon the toggling of a data strobe signalDOS. The data is input/output through the data input/output pin by a DDR(double data rate) transmission method. The NAND flash memory furtherincludes a command/address buffer receiving the command and addresstransmitted through command/address pin. The NAND flash memory furtherincludes a control unit controlling the reception of the command andaddress. The control unit receives a chip enable signal nCE and a loadsignal nLOAD from a flash controller and controls the reception of thecommand and address

In some exemplary embodiments of the present invention, there areprovided flash memory systems including a flash controller and a flashmemory module formed of a plurality of NAND flash memories. Each of theNAND flash memories includes a memory cell array used for storing data,a command/address pin through which a command and an address arereceived from the flash controller for inputting/outputting data to/fromthe memory cell array and a data input/output pin through which data areinput to and output from the memory cell array.

In some exemplary embodiments, each of the NAND flash memories furtherincludes a status register receiving a status read command through thecommand/address pin and providing an operational status of the NANDflash memory to the flash controller. The flash controller sends thestatus read command to the NAND flash memory when the NAND flash memoryoperates, before the NAND flash memory operates or after the NAND flashmemory operates. The status register sends a status signal SQ to theflash controller to inform the flash controller whether the NAND flashmemory is internally operational. The flash controller controls theinternal operation of the NAND flash memory in response to the statussignal SQ. The data input/output through the data input/output pin isperformed according to a toggling of a data strobe signal DQS. The datainput/output through the data input/output pin is performed by a DDRtransmission method. Each of the NAND flash memories further includes acommand/address buffer receiving the command and address transmittedthrough command/address pin. Each of the NAND flash memories furtherincludes a control unit controlling the reception of the command andaddress. The control unit receives a chip enable signal nCE and a loadsignal nLOAD from the flash controller and controls the reception of thecommand and address.

BRIEF DESCRIPTION OF THE FIGURES

The above and other features of the present disclosure will become moreapparent by describing in detail exemplary embodiments of the presentinvention with reference to the attached drawings in which:

FIG. 1 illustrates a conventional NAND flash memory;

FIG. 2 is a table illustrating pins of the NAND flash memory of FIG. 1;

FIG. 3 is a block diagram illustrating a flash memory system with amulti-bank architecture using the NAND flash memory of FIG. 1;

FIG. 4 illustrates an NBX NAND flash memory according to an exemplaryembodiment of the present invention;

FIG. 5 is a table providing descriptions of pins of the NBX NAND flashmemory of FIG. 4, according to an exemplary embodiment of the presentinvention;

FIG. 6 is a block diagram of an NBX NAND flash memory systemillustrating the NBX NAND flash memory of FIG. 4, according to anexemplary embodiment of the present invention;

FIG. 7 is a timing diagram showing how data are erased from the NBX NANDflash memory of FIG. 6, according to an exemplary embodiment of thepresent invention;

FIG. 8 is a timing diagram for explaining how data are written into theNBX NAND flash memory of FIG. 6, according to an exemplary embodiment ofthe present invention;

FIG. 9 is a timing diagram for explaining how data are read from the NBXNAND flash memory of FIG. 6, according to an exemplary embodiment of thepresent invention;

FIG. 10 is a diagram illustrating an NBX NAND flash memory systemaccording to an exemplary embodiment of the present invention;

FIG. 11 is a block diagram illustrating an NBX flash module of the NBXNAND flash memory system of FIG. 10, according to an exemplaryembodiment of the present invention;

FIG. 12 is a block diagram illustrating an internal structure of the NBXflash module of FIG. 11, according to an exemplary embodiment of thepresent invention;

FIGS. 13 through 15 are timing diagrams illustrating a bank interleavingoperation of the NBX flash memory system of FIG. 10, according to anexemplary embodiment of the present invention;

FIG. 16 illustrates a thin small outline package (TSOP) of an NBX NANDflash memory according to an exemplary embodiment of the presentinvention; and

FIG. 17 is a table illustrating pins of the TSOP of FIG. 16, accordingto an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstructed as limited to the exemplary embodiments set forth herein.

FIG. 4 illustrates a NAND flash memory 300 according to an exemplaryembodiment of the present invention, and FIG. 5 is a table illustratingpins of the NBX NAND flash memory 300 according to an exemplaryembodiment of the present invention. The NAND flash memory 300 includesadditional command/address pins C/A0 to C/A3. The NAND flash memory 300further includes a data strobe pin DQS in addition to data input/outputpins DQ0 to DQ7 for input/output data synchronization. Input signals ofthe NAND flash memory 300 are synchronized with a clock (CLK) signal.The NAND flash memory 300 of FIG. 4 will now be referred to as a NANDbus scalable (NBX) NAND flash memory.

Referring to FIG. 5, the command/address pins C/A0 to C/A3 are used forinputting command and address signals. Although four command/addresspins C/A0 to C/A3 are shown in FIG. 5, the number of command/addresspins C/A0 to C/A3 can be increased. The nLOAD pin is used for loading acommand or address signal to the NAND flash memory 300. The nCE pin is achip enable pin. The CLK pin is a clock pin. The Vcc pin is a powervoltage pin, and the Vss pin is a ground voltage pin.

The SQ pin indicates which operation is being performed or is completedin the NBX NAND flash memory 300. For example, a high SQ signalindicates that an operation is completed in the NBX NAND flash memory300 and the NBX NAND flash memory 300 is ready for the next operation. Alow SQ signal indicates that an operation is being performed in die NBXNAND flash memory 300. The SQ signal is output in synchronization with aCLK signal. As described above, the DQS pin is a data strobe pin usedfor data input/output, and the DQ0 to DQ7 pins are data input/outputpins.

FIG. 6 is a block diagram of an example of the NBX NAND flash memory ofFIG. 4, according to an exemplary embodiment of the present invention.The NBX NAND flash memory 420 is electrically connected to a flashcontroller 410. The NBX NAND flash memory 420 receives address andcommand signals from the flash controller 410 through a C/A pin andreceives data from and sends data to the flash controller 410 through adata input/output pin.

Referring to FIG. 6, the NBX NAND flash memory 420 includes a memorycell array 421, a command address buffer 422, a page buffer 423, a datainput/output circuit 424, a control unit 425, and an SQ register 426.

The memory cell array 421 includes a plurality of memory blocks (notshown). Each of the memory blocks includes a plurality of pages (notshown). Each of the pages includes a plurality of memory cells thatshare a word line. The size of each page may be 512 bytes, 2 KB, or 4KB, The size of page varies according to the type of the flash memory.In the NBX NAND flash memory 420, data are erased in units of a block,and data are read and written in units of a page.

The command address buffer 422 is connected to the memory cell array 421through a word line WL. The command address buffer 422 receives acommand or address signal from the flash controller 410. The controlunit 425 receives control signals nCE and nLOAD and controls the commandaddress buffer 422.

The command signal is input to the NBX NAND flash memory 420 when thecontrol signals nCE and nLOAD are low. Table 1 shows examples of commandand control signals used in the NBX NAND flash memory system 400. InTable 1, nCKE denotes a clock enable signal.

TABLE 1 Comman d(4bits) Code nCKE nCE nLOAD DQS DQ Clock Cycle Chip — LH X High-Z High-Z L −> H Deselect Clock — H X X High-Z X X(after ncycles) Stop Power — H H X High-Z High-Z Stead State After n On cyclesRead 0h L L L High-Z High-Z L −> H, 1^(st) cycle: Read in (after thataddress in) Read 1h L L L Toggle Data L −> H, 1^(st) cycle: Read Enableout enable (after that read data out) Program 2h L L L High-Z High-Z L−> H, 1 cycle: Program (White) Command (after that address in) Program3h L L L Toggle Data- L −> H, 1^(st) cycle: Enable in command in (afterthat program the page) Page 4h L L High-Z High-Z L −> H, 1 cycle ReadStop Page 5h L L High-Z High-Z L −> H, 1 cycle Write Stop ID Read 6h L LToggle Data L −> H, 1^(st) cycle: cmd in Out Register 7h L L Toggle DataL −> H, 1^(st) cycle: cmd in Configuration In (after that configurationfor n cycles) Status 8h — — High-Z High-Z L −> H, 1^(st) cycle: cmd in,Read 2^(nd) cycle: status data out Reserved 9h-Eh Reset Fh L L High-ZHigh-Z After n cycles

Referring to Table 1, Read is a command for starting a read operation.Read Enable is a command for reading data. Write is a command forstarting a write operation. Write Enable or Program Enable is a commandfor writing data into the memory cell array 421.

Status Read is a command for checking the operation status of the NBXNAND flash memory 420. Reset is a command for initializing the NBX NANDflash memory 420.

For example, a read command is input to the NBX NAND flash memory 420 inone clock cycle when nCE and nLOAD signals are low. Next, an address isinput to the NBX NAND flash memory 420. Other commands are input to theNBX NAND flash memory 420 in the same manner.

Referring again to FIG. 6, the NBX NAND flash memory 420 includes the SQregister 426. The SQ register 426 stores the status of the NBX NANDflash memory 420. When a status read command is input, the SQ register426 sends a status signal SQ to the flash controller 410 under thecontrol of the control unit 425.

The status signal SQ is sent to the flash controller 410 to inform theflash controller 410 of the status of the NBX NAND flash memory 420. Forexample, when the NBX NAND flash memory 420 does not perform anyoperation, the status signal SQ is high, and when the NBX NAND flashmemory 420 performs an operation, the status signal SQ is low. Thestatus signal is generated in synchronization with a CLK signal.Referring to Table 1, after a status read command is input and one cyclepasses, a state signal SQ is output. The flash controller 410 canprovide the status signal SQ to the flash memory at anytime.

An address is input from the first clock cycle after a command is input.The bit size of the address is determined by an nLOAD signal. Erase,write, and read operations of the NBX NAND flash memory 420 of FIG. 6will now be described with reference to FIGS. 7 through 9.

FIG. 7 is a timing diagram illustrating how data are erased from the NBXNAND flash memory 420 of FIG. 6, according to an exemplary embodiment ofthe present invention. Referring to FIG. 7, when an nCE signal and annLOAD signal are low, a command or an address is input through a C/Apin.

Referring to FIG. 7, S denotes a status read command, E denotes an erasecommand, A denotes an address, and EE denotes an erase enable command.The status read command S can be input regardless of whether an eraseoperation is performed. When the status read command S is input, the NBXNAND flash memory 420 generates a status signal SQ after one clockcycle.

The NBX NAND flash memory 420 starts a read operation in response to anerase command. When an erase command is input, an address A is inputthrough the C/A pin. After the address is completely input, an eraseenable command EE is input. The NBX NAND flash memory 420 erases datafrom a memory block corresponding to the address A in response to theerase enable command EE.

During the erase operation, the NBX NAND flash memory 420 generates astatus signal SQ in response to a status read command S to indicate itsstatus (erase status). After the erase operation, the NBX NAND flashmemory 420 generates a status signal SQ in response to a status readcommand S to indicate its status (end of erase operation).

FIG. 8 is a timing diagram for explaining how data are written into theNBX NAND flash memory 420 of FIG. 6, according to an exemplaryembodiment of the present invention. Referring to 8, when an nCE signaland an nLOAD signal are low, a command or an address is input through aC/A pin.

In FIG. 8, W denotes a write command, A denotes an address, and WEdenotes a write enable command. Here, a status read command S can beinput regardless of whether a write operation is performed. When thestatus read command S is input, the NBX NAND flash memory 420 generatesa status signal SQ after one clock cycle.

The NBX NAND flash memory 420 starts a write operation in response to awrite command W. After a write command W and an address A are input, awrite enable command WE is input. After that, the NBX NAND flash memory420 receives data through a data input/output (DQ) pin according to thetoggling of a data strobe (DQS) signal. Data are input to or output fromthe NBX NAND flash memory 420 in synchronization with the DQS signal.Referring to FIG. 8, data are transferred twice per one period of theDQS signal by a double data rate (DDR) transmission method.

After the data are received, the NBX NAND flash memory 420 performsprogramming on a page corresponding to the address A using the receiveddata. During the write operation, the NBX NAND flash memory 420generates a status signal SQ in response to a status read command S toindicate its status (write status). After the write operation, the NBXNAND flash memory 420 generates a status signal SQ in response to astatus read command S to indicate its status (end of write operation).

FIG. 9 is a timing diagram for explaining how data are read from the NBXNAND flash memory 420 of FIG. 6, according to an exemplary embodiment ofthe present invention. In FIG. 9, R denotes a read command, A denotes anaddress, and RE denotes a read enable command. A status read command Scan be input regardless of whether a read operation is performed. Whenthe status read command S is input, the NBX NAND flash memory 420generates a status signal SQ after one clock cycle.

The NBX NAND flash memory 420 starts a read operation in response to aread command R. After a read command R and an address A are input, the420 reads data from a page corresponding to the address A and stores thedata in the page buffer 423 (refer to FIG. 6). The NBX NAND flash memory420 outputs a status signal SQ in response to a status read command Sindicating that the NBX NAND flash memory 420 is ready for datatransmission.

The NBX NAND flash memory 420 outputs the data stored in the page buffer423 in response to a read enable command RE. The NBX NAND flash memory420 outputs the data through a DQ pin according to the toggling of a DQSsignal. Data are output from the NBX NAND flash memory 420 insynchronous with the DQS signal. Referring to FIG. 9, data are read fromthe NBX NAND flash memory 420 at double data rate (DDR).

As explained above, the NBX NAND flash memory of the present inventionincludes separate C/A and DQ pins. Furthermore, the NBX NAND flashmemory includes the SQ register to generate a status signal SQ wheneverthe flash controller sends a status read command S. Since the CA pin andthe DQ pin are separate, read and write speeds can be increased.Furthermore, command and address buses can have a width different fromthat of a data bus.

FIG. 10 is a diagram illustrating an NBX NAND flash memory system 500according to an exemplary embodiment of the present invention. Referringto FIG. 10, the NBX NAND flash memory system 500 includes a flashcontroller 550 and a plurality of NBX flash modules 510, 520, 530, and540. In the exemplary embodiment of FIG. 10, four NBX flash modules areillustrated.

The NBX flash modules 510, 520, 530, and 540 are connected to flashsockets 501, 502, 503, and 504, respectively, and the flash sockets 501,502, 503, and 504 are connected to the flash controller 550 through adata bus (DQ bus). The NBX flash modules 510, 520, 530, and 540 receivea bank selection (nBS) signal from the flash controller 550.Furthermore, data (DQ) and control (CTRL) signals are transmittedbetween the flash controller 550 and the NBX flash modules 510, 520,530, and 540. Each of the NBX flash modules 510, 520, 530, and 540includes a plurality of NBX NAND flash memories. In the exemplaryembodiment shown in FIG. 10, each of the NBX flash modules 510, 520,530, and 540 includes sixteen NBX NAND flash memories 511.

The flash controller 550 controls write, read, and erase operations ofthe NBX NAND flash memories of the NBX flash modules 510, 520, 530, and540. Furthermore, the flash controller 550 performs bank interleavingbetween banks using the nBS signal.

When it is necessary to update SQ registers of the NBX NAND flashmemories of the NBX flash modules 510, 520, 530, and 540, the flashcontroller 550 can transmit a register value that can be commonly usedfor all the NBX flash modules 510, 520, 530, and 540. This function ofthe flash controller 550 is referred to as a broadcasting function.After simultaneously enabling nBS signals for all banks, the flashcontroller 550 provides a register configuration command (refer to Table1). The register configuration command is simultaneously provided toeach of the NBX NAND flash memories through a C/A pin. Then, the flashcontroller 550 writes a register value to an SQ register using the C/Apin.

FIG. 11 is a block diagram illustrating an NBX flash module of the NBXNAND flash memory system 500 of FIG. 10, according to an exemplaryembodiment of the present invention. in FIG. 11, reference numeral 510 adenotes a front surface of the NBX flash module 510 of the NBX NANDflash memory system 500, and reference numeral 510 b denotes a backsurface of the NBX flash module 510.

Referring to FIGS. 11( a) and (b), eight NBX NAND flash memories 511 aare formed in the front surface 510 a of the NBX flash module 510, andeight NBX NAND flash memories 511 b are formed on the back; surface 510b of the NBX flash module 510. The eight NBX NAND flash memories 511 aform one bank, and the eight NBX NAND flash memories 511 b form anotherbank. For example, one NBX flash module includes two banks. When each ofthe NBX NAND flash memories 511 a and 511 b has an 8-bit bus width, onebank has a 64-bit bus width.

An electrically erasable programmable read only memory (EEPROM) 512 forstatus presence detection (SPD), a clock buffer 513, a buffer 514 forC/A and control signals, and an interface 516 a are formed on the frontsurface 510 a of the NBX flash module 510. The EEPROM 512 is used tostore data (SPD data) necessary for the flash controller 550 (refer toFIG. 10) to access the NBX flash module 510. The clock buffer 513 isused for distributing a clock signal to the NBX NAND flash memories 511a and 511 b. The buffer 514 is used for distributing command, address,and control signals to the NBX NAND flash memories 511 a and 511 b.

Fast enable transfer (PET) switches 515 and an interface 516 b areformed on the back surface 510 b of the NBX flash module 510. The FETswitches 515 are used to reduce loads on data buses, thereby enablinghigh-speed data transmission. Since a DDR transmission method is usedfor the NBX NAND flash memories 511 a and 511 b, the FET switches 515are used to facilitate the use of the DDR transmission method. Each ofthe FET switches 515 can latch 10 bits: 8 bits for data (DQ), 1 bit fora DQS signal, and 1 bit for a SQ signal. When assembled, the interfaces516 a and 516 b of the NBX flash module 510 are connected to the flashsocket 510 (refer to FIG. 10).

FIG. 12 is a block diagram illustrating an internal structure of the NBXflash module 510 of FIG. 11, according to an exemplary embodiment of thepresent invention. As illustrated in FIG. 11, the NBX flash module 510includes the NBX NAND flash memories 511 a and 511 b (first and secondbanks), the EEPROM 512 for SPD, the clock buffer 513, the buffer 514 forC/A and control signals, the FET switches 515, and the interface 516.

The interface 516 receives a command, an address, data, first and secondbank selection signals nBS1 and nBS2, and an nLOAD signal from the flashcontroller 550 (refer to FIG. 10). Here, the nBS1 signal is used forselecting the first bank 511 a, and the nBS2 signal is used forselecting the second bank 511 b.

The nBS1 signal is provided as a chip enable signal nCE for the NBX NANDflash memories of the first bank 511 a. The nBS2 signal is provided as achip nCE signal for the NBX NAND flash memories of the second bank 511b. The buffer 514 for C/A and control signals is used to temporarilystore a command, an address, and an nLOAD signal and sends them to aselected bank.

The clock buffer 513 receives a clock signal nCLK and generates firstand second clock signals CLK1 and CLK2. The first clock signal CLK1 isprovided to the first bank 511 a, and the second clock signal CLK2 isprovided to the second bank 511 b. Furthermore, the clock buffer 513provides a clock signal for the buffer 514 for C/A and control signals.The buffer 514 is operated in synchronization with a clock signal.

The EEPROM 512 for SPD stores SPD information necessary for the flashcontroller to access the NBX flash module 510 For example, the EEPROM512 for SPD stores information about internal delay time necessary forwriting data to or reading data from the NBX NAND flash memories of thefirst and second banks 511 a and 511 b. In read or write operation, theflash controller 550 reads the internal delay time information from theEEPROM 512 and outputs signals and data according to the readinformation for read or write operation.

NBX NAND flash memories included in a given bank have the same pagesize. Information about this page size is stored in the EEPROM 512. Thepage size of a NBX NAND flash memory may vary from one bank to anotherbank and/or from one NBX flash module to another NBX flash module. TheEEPROM 512 for SPD stores this page information. When accessing a NBXflash module, the flash controller 550 reads the page information fromthe EEPROM 512 and operates according to the read page information.

Banks included in one NBX flash module can have different storagecapacities. In addition, NBX NAND flash memories included in one bankcan have different storage capacities. The EEPROM 512 for SPD storesinformation about the bank capacities of banks. When accessing a NBXflash module, the flash controller 550 reads the bank capacityinformation from the EEPROM 512 and operates according to the read bankcapacity information. That is, the flash controller 550 reads SPDinformation from the EEPROM 512 and sets itself using the SPDinformation.

FIGS. 13 through 15 are timing diagrams for explaining a bankinterleaving operation of the NBX NAND flash memory system 500 of FIG.10, according to an exemplary embodiment of the present invention. Bankinterleaving is a read, write, or erase operation that is performedalternately on banks. FIG. 13 illustrates an interleaving operationbetween banks for reading data from the banks. FIG. 14 illustrates aninterleaving operation between banks for writing data to the banks. FIG.15 illustrates an interleaving operation between banks for erasing,writing, and reading.

Referring to FIG. 13, a first bank is enabled by a first bank selectionsignal nBS1. For example, when the first bank, selection signal nBS1 isat a low level, data are read from the first bank. Reading data from thefirst bank starts in response to a read command R. After the readcommand R and an address A is input, data are read from a selected pageand transmitted to a page buffer. When data corresponding to one page isstored in the page buffer, an NBX NAND flash memory outputs a statussignal SQ in response to a status read command S to indicate that it isready to output data.

The NBX NAND flash memory outputs the data stored in the page buffer inresponse to a read enable command RE. Here, the NBX NAND flash memoryoutputs the data through a data input/output pin DQ according to thetoggling of a data strobe signal DQS.

When a second bank selection signal nBS2 is changed to a low levelduring the reading operation for the first bank, data are read from asecond bank. Similarly, when a third bank selection signal nBS3 ischanged to a low level during the reading operations for the first andsecond banks, data are read from a third bank. The reading operationsfor the second and third banks are performed in the same manner as thatfor the first bank.

After data are output from the first bank, data are output from thesecond bank without a delay time. Similarly, after data are output fromthe second bank, data are output from the first bank.

Referring to FIG. 14, when a first bank selection signal nBS1 is at alow level, data are written into a first bank. Writing data into thefirst bank starts in response to a write command W. After the writecommand W and an address A are input, a write enable command WE isinput. An NBX NAND flash memory receives data through a datainput/output pin DQ according to the toggling of a data strobe signalDQS. The received data are stored in a page buffer.

After data are stored in the page buffer, the NBX NAND flash memoryperforms internal programming on a page of the address A using thestored data. The NBX NAND flash memory outputs a status signal SQ inresponse to a status read command S to indicate the end of the writeoperation.

When second and third bank selection signals are changed to a low levelduring the write operation for the first bank, data are written intosecond and third banks. The write operations for the second and thirdbanks are performed in the same manner as that for the first bank.

Referring to FIG. 14, after data are completely loaded from a flashcontroller to a page buffer of the first bank, data are loaded from theflash controller to a page buffer of the second bank without a delaytime. Similarly, after the data are loaded to the page buffer of thesecond bank, data are loaded from the flash controller to a page bufferof the third bank.

Referring to FIG. 15, an erase operation is performed on a first bank, awrite operation is performed on a second bank, and a read operation isperformed on a third bank. During the erase operation for the firstbank, the write operation for the second bank is performed. In addition,during the erase and write operations for the first and second banks,the read operation for the third bank is performed.

Since a conventional NAND flash memory uses a data input/output pin DQfor receiving command and address signals as well as data, a data streamin a data bus or channel is often interrupted. Furthermore, aconventional NAND flash memory module has a long data delay time duringan bank interleaving operation. However, as illustrated in FIGS. 13through 15, the NBX flash module of exemplary embodiments of the presentinvention can perform an interleaving operation for data input/outputwithout a data delay time, so that data can be read from and written tothe NBX flash module at a high speed.

FIG. 16 illustrates a thin small outline package (TSOF) of an NBX NANDflash memory according to an exemplary embodiment of the presentinvention, and FIG. 17 is a table providing descriptions of pins of theTSOP of FIG. 16, according to an exemplary embodiment of the presentinvention. Referring to FIG. 16, the NBX NAND flash memory has 48 pins.The 1st to 24th pins are formed on the left side, and the 25th to 48thpins are formed on the right side. Referring to FIG. 17, all controlfunctions are assigned to the left-side pins. According to exemplaryembodiments of the present invention, the number of pins can bedecreased, and the NBX NAND flash memory can be designed to have allcontrols pins on one side. Therefore, the NBX NAND flash memory can havea simple structure.

As described above, in the NAND flash memory of exemplary embodiments ofthe present invention, the C/A pin is separated from the datainput/output pin. Therefore, data input/output speed can be improved.Furthermore, the NAND flash memory can perform a bank interleavingoperation with less delay time.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive. It will be understood by those of ordinary skill in theart that various changes in form and details may be made withoutdeparting from the spirit and scope of the present invention.

1. A NAND flash memory comprising: a memory cell array storing data; acommand/address pin through which a command and an address are receivedfor transmitting data; and a data input/output pin through which dataare transmitted in the memory cell array.
 2. The NAND flash memory ofclaim 1, further comprising a status register receiving a status readcommand through the command/address pin and providing an operationalstatus of the NAND flash memory to a flash controller.
 3. The NAND flashmemory of claim 2, wherein the flash controller sends the status readcommand to the NAND flash memory.
 4. The NAND flash memory of claim 2,wherein the status register sends a status signal SQ to the flashcontroller to inform the flash controller whether the NAND flash memoryis internally operational.
 5. The NAND flash memory of claim 4, whereinthe flash controller controls the internal operation of the NAND flashmemory in response to the status signal SQ.
 6. The NAND flash memory ofclaim 1, wherein the data transmitted through the data input/output pinis transmitted according to a toggling of a data strobe signal DQS. 7.The NAND flash memory of claim 6, wherein the data transmitted throughthe data input/output pin is transmitted by a DDR (double data rate)transmission method.
 8. The NAND flash memory of claim 1, furthercomprising a command/address buffer receiving the command and addressreceived through command/address pin.
 9. The NAND flash memory of claim8, further comprising a control unit controlling the reception of thecommand and address.
 10. The NAND flash memory of claim 9, wherein thecontrol unit receives a chip enable signal nCE and a load signal nLOADfrom a flash controller and controls the reception of the command andaddress.
 11. A flash memory system comprising: a flash controller, and aflash memory module comprising a plurality of NAND flash memories,wherein each of the NAND flash memories comprises: a memory cell arraystoring data; a command/address pin through which a command and anaddress are received from the flash controller for transmitting data inthe memory cell array; and a data input/output, pin through which datais transmitted in the memory cell array.
 12. The flash memory system ofclaim 11, wherein each of the NAND flash memories further comprises astatus register receiving a status read command through thecommand/address pin and providing an operational status of the NANDflash memory to the flash controller.
 13. The flash memory system ofclaim 12, wherein the flash controller sends the status read command tothe NAND flash memory.
 14. The flash memory system of claim 12, whereinthe status register sends a status signal SQ to the flash controller toinform the flash controller whether the NAND flash memory is internallyoperational.
 15. The flash memory system of claim 14, wherein the flashcontroller controls the internal operation of the NAND flash memory inresponse to the status signal SQ.
 16. The flash memory system of claim11, wherein the data transmitted through the data input/output pin istransmitted according to a toggling of a data strobe signal DQS.
 17. Theflash memory system of claim 16, wherein the data transmitted throughthe data input/output pin is transmitted by a DDR (double data rate)transmission method.
 18. The flash memory system of claim 1, whereineach of the NAND flash memories further comprises a command/addressbuffer receiving the command and address received throughcommand/address pin.
 19. The flash memory system of claim 18, whereineach of the NAND flash memories further comprises a control unitcontrolling the reception of the command and address.
 20. The flashmemory system of claim 19, wherein the control unit receives a chipenable signal nCE and a load signal nLOAD from the flash controller andcontrols the reception of the command and address.